An integrated circuit (IC), such as a general purpose integrated circuit, system on a chip (SOC), application specific integrated circuit (ASIC), and the like, may include cells and connections between cells formed as a semiconductor. Because of the vast range of functionality desired by manufacturers and users of integrated circuits, an extensive number of cells may be needed having complex connections between the cells.
A cell may be thought of as a functional element of a circuit provided to perform a desired function. Each cell may include one or more circuit elements such as transistors, capacitors, and other circuit elements grouped to perform the desired function. Each of the cells of an integrated circuit may have one or more pins, each of which may be connected to one or more other pins of the integrated circuit by wires. The wires connecting the pins of the integrated circuit are also formed on the surface of the chip.
A net is a set of two or more pins which are connected. Because of the vast number of pins that may be included in an integrated circuit and the variety of connections needed to communicatively couple the pins, a chip also includes definitions describing the pins and interconnects. Typically, all the pins of a net are connected. Generally, the number of nets of a chip is in the same order as the number of cells on that chip. A majority of nets include an interconnection between two pins, although nets may include much greater numbers of pins. A netlist is a list of nets for a chip.
Integrated circuits formed as chips are generally configured as a large number of electronic components fabricated by layering several different materials on a silicon base, such as a wafer. The design of an integrated circuit may be described geometrically as a layout. For instance, a layout may include a set of planar geometric shapes in several layers.
A layout is typically checked to ensure that all of the design requirements are met. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files may then be converted into pattern generator files that are used to produce patterns called masks by a pattern generator, which may include optical, electron beam, and the like generation methods.
Due to the large number of components included in an integrated circuit, the decreasing size of geometric features utilized to provide functionality, and the details required by the fabrication process, the physical design process is typically performed utilizing information handling systems, such as computers and servers. Through use of these systems, the physical design process may proceed to determine an arrangement of devices, such as in a plane and/or in three dimensional space, as well as efficient interconnection and routing schemes between devices to obtain the desired functionality.
In the layout design process, typically, the input to the physical design is a circuit diagram, and the output is the layout of the circuit. This may be accomplished in several stages, including partitioning, floor planning, placement, routing and compaction.
For instance, a chip may include several million transistors. Thus, layout of the entire circuit, in certain instances, may not be handled due to limitations of memory space and computational power. Therefore, the layout may be partitioned by grouping the components into blocks, such as sub-circuits and modules. The actual partitioning process may consider a variety of factors, such as size of blocks, number of blocks, number of interconnections, and the like. The output of partitioning is a set of blocks with interconnections between the blocks, which may be described as a netlist.
Floor planning and placement may include the selection of layout alternatives for each block of a chip, as well as between blocks and to edges. During placement, the blocks are positioned on the chip, preferably in such a manner as to find a minimum area arrangement for the blocks that allows completion of interconnections between the blocks.
The routing phase completes the interconnections between blocks according to the specified netlist. For instance, space not occupied by block, which may be referred to as routing space, may be partitioned into regions called channels. Preferably, the router completes all circuit connections using the shortest possible wire length and uses only the channels.
To calculate the performance of integrated circuits, designers compute the delays of the cells in the integrated circuit. A variety of delays may be considered without departing from the spirit and scope of the present invention. For instance, a propagation delay of a cell may be defined as the time duration a signal takes to travel from an input to an output of a cell. The measurement point at the input is called the switching threshold. A propagation delay of a cell may be defined for every input to output pin combination of a cell under both rising and falling input conditions. The propagation delay is also affected by a given process (P), voltage (V) and temperature (T). Another type of delay is the setup-hold time delay which is an input constraint for sequential cells. The setup time is defined as the time duration a data signal is required to be available at the input of a cell before the clock signal transition, and the hold time is defined as the time duration a data signal is required to be stable after the clock signal transition.
Therefore, it would be desirable to provide a system and method to increase the efficiency of design and implementation of an integrated circuit.